The Cause

Until relatively recent times digital PCB design (and especially when prototyping) could be viewed as simply a means to electrically interconnect components and unless you designed RF circuits there was little else to worry about. However the PCB itself, or the means of connecting the components used (i.e. prototyping), is now is a very common cause of a loss of signal integrity. The reason is mainly due to the rise and fall times of output signals having decreased as devices are designed to operate faster and faster and to use smaller and smaller silicon manufacturing processes. This problem is not actually due to the operating frequency of a device or the frequency at which a signal is changing, it is due to the speed at which a signal output changes state from high to low and low to high. A signal doesn’t instantaneously change from high to low or low to high, it takes a certain amount of time which will be specified as the rise and fall time in a devices data sheet. Previous signal rise and fall times of many 10’s of nano seconds have now become times measured in just a few nano seconds or for many devices they are measured in pico seconds.

So you may be thinking, this can’t possibly be an issue for me, my board is only operating at a few MHz and I’ve even slowed my data bus down to a few KHz. Well unfortunately that doesn’t matter. If you work with a DC signal the only thing you really care about in a wire or PCB track is its resistance, which for short lengths will be close to zero. However, when using that wire or PCB track with a fast AC signal it starts to behave like a capacitor and inductor. Capacitors and inductors exhibit resistance to alternating current called reactance. The impedance of the wire or track is the vector sum of resistance and reactance, essentially the total resistance seen at a particular frequency. What happens when you send a signal with a fast rising and falling edge down a wire or PCB track, if the impedance of the gate driving the wire or track isn’t exactly the same as the one receiving the it, is it that some of the pulse bounces (literally) back to the driving gate. As there is still an impedance mismatch, the signal continues to bounce between the two until it finally dampens out. This bouncing becomes worse as the speed of signal rise and fall times increases. Basically, the faster rise and fall times of signals from modern semiconductors combined with wire or PCB trace inductance and capacitance causes noise signals of a greater magnitude than before. Greater magnitude means the bouncing signals can reach the threshold voltage required for the receiving device to ‘see’ another clock pulse, or an incorrect data level at the moment it is sampling the data line.  The solution is to design your PCB to use impedance controlled tracks on these clocked connections.

Single Connections

Download the free Saturn PCB Design Toolkit – its a great tool for this.  Use it as follows:

Select Conductor Impedance

Select Imperial or Metric (you can select later and it will auto convert all values)
Set copper weights and plating thickness (e.g. 18um copper + 18um plating = 35micros (1oz))
Select internal or external layers (typically microstrip or embedded microstrip)
Enter substrate options (prepreg dielectric constant – typical PCB’s are FR4)
Enter track width in conductor width
Enter prepreg height in conductor height (the distance between the copper layers excluding their thickness)
Click ‘solve’
Now adjust the track width until you get the impedance (Zo) you need.  This is the thickness to make your tracks

100ohm Single Track Impedance (General signals, SPI bus etc)

General signals, SPI bus, etc will generally perform well with a 100ohm track Impedance.  Some examples track widths with a GND plane under the tracks:

2 layer 1.6mm PCB (1.48mm FR4) = 0.61mm (100.3150ohms)

4 layer PCB Pool – Internal to Internal (0.71mm FR4) = 0.27mm (100.2273ohms)

4 layer PCB Pool – Internal to External (0.38mm FR4) = 0.12mm (100.9915ohms), or if too small then 0.15mm = (95.0631ohms)

4 layer PCB Train – Internal to Internal (0.99mm FR4) = 0.4mm (99.8636ohms)

4 layer PCB Train – Internal to External (0.22mm FR4, layer 2-3) = 0.05mm – not possible

4 layer PCB Train – Internal to External (1.245mm FR4, layer 1-3) = 0.49mm – not possible

75ohm Single Track Impedance

Also relevant to 75ohm radio antenna connections.Example track widths with GND plane under track

2 layer 1.6mm PCB (1.48mm FR4) = 1.29mm (75.0457ohms)

4 layer PCB Pool – Internal to Internal (0.71mm FR4) = 0.6mm (74.7938ohms)

4 layer PCB Pool – Internal to External (0.38mm FR4) = 0.3mm (74.8156ohms)

50ohm Single Track Impedance

Also relevant to 50ohm radio antenna connections.  Example track widths with GND plane under track

2 layer 1.6mm PCB (1.48mm FR4) = 2.65mm (50.1165ohms)

4 layer PCB Pool – Internal to Internal (0.71mm FR4) = 1.25mm (50.0581ohms)

4 layer PCB Pool – Internal to External (0.38mm FR4) = 0.65mm (49.9609ohms)

Differential Pairs

Download the free Saturn PCB Design Toolkit – its a great tool for this.  Use it as follows:

Select Differential Pairs

Select Imperial or Metric (you can select later and it will auto convert all values)
Set copper weights and plating thickness (e.g. 18um copper + 18um plating = 35micros (1oz))
Select internal or external layers (typically microstrip or embedded microstrip)
Enter substrate options (prepreg dielectric constant – typical PCB’s are FR4)
Enter track width in conductor width
Enter clearance between tracks in conductor distance
Enter prepreg height in conductor height (the distance between the copper layers excluding their thickness)
Click ‘solve’
Now adjust the track width and spacing until you get the impedance (Zdifferentail) you need.  This is the thickness to make your tracks

USB 90ohm Differential Pair Track Impedance

USB 2.0 requires 90ohms differential impedance (max 45ohms per track)

Max trace-length mismatch between High-speed USB signal pairs should be no greater than 3.81mm.

Example track widths with GND plane under track

4 layer PCB Pool – Internal to External (0.38mm height – FR4 thickness to GND plane)

35um copper, track spacing 0.15mm and 0.38mm track width = 90.525ohms Zdifferential
35um copper, track spacing 0.2mm and 0.43mm track width = 90.174ohms Zdifferential

To stick with the max 45ohms per track (not practical for many designs):
35um copper, track spacing 1.4mm and 0.75mm track width = 89.118ohms Zdifferential

4 layer PCB Pool – Internal to Internal (0.71mm height – FR4 thickness to GND plane)

35um copper, track spacing 0.15mm and 0.61mm track width = 90.385ohms Zdifferential

4 layer PCB Train – Internal to Internal (0.99mm height – FR4 thickness to GND plane)

35um copper, track spacing 0.15mm and 0.8mm track width = 90.156ohms Zdifferential

2 layer 1.6mm PCB (1.48mm FR4 thickness to GND plane)

35um copper, track spacing 0.15mm and 1.12mm track width = 90.184ohms Zdifferential

10/100Mbps Ethernet 100ohm Differential Pair Track Impedance

Ethernet requires 100ohms differential impedance (max 50ohms per track)

Example track widths with GND plane under track

4 layer PCB Pool – Internal to External (0.38mm height – FR4 thickness to GND plane)

35um copper, track spacing 0.15mm and 0.3mm track width = 100.462ohms Zdifferential
35um copper, track spacing 0.2mm and 0.34mm track width = 100.923ohms Zdifferential

To stick with the max 50ohms per track (not practical for many designs):
35um copper, track spacing 2.5mm and 0.65mm track width = 99.835ohms Zdifferential
If you use 1 of the plane layers with GND above and below (0.71mm & 0.38mm from track to GND planes) you get:
35um copper, track spacing 1.5mm and 0.42mm track width = 99.0.16ohms Zdifferential

Ensure Your PCB IS Made With The Right Stackup

Its a good idea to include the required stackup on one of your copper layers to ensure it is used.  Something like this:

http://www.analog.com/library/analogdialogue/archives/41-06/ground_bounce.html

Buck DCDC Converters

This is bad:

This is good:

Boost DCDC Converters

Ground Bounce Design Tips

Switcher IC’s with internal mosfets tend to aim towards higher efficiency and therefore lower mosfet on resistance.  However low on resistance means faster switching times, which contributes to noise and ground bounce.  Should you consider a less efficient IC with a higher on resistance?  You can’t easily add resistance externally as the resistance your aiming for is still very low (e.g. 100 or more milli Ohms).

For a boost design get the output capacitor cathode right next to the switchers mosfet ground pin.  A few extra mm of tracking can cause issues on some designs.  Keep the inductor to diode and diode to capacitor tracking very short.

Can you shut-down the DCDC converter while doing sensitive measurements?  If your doing periodic fast AtoD readings then whilst not an ideal solution, including the means to shut-down the DCDC converter whilst the AtoD is sampling can be a compromise solution in suitable applications.

High Current Design Tips

If changing layers for any of the tracking, including the power supply to the switcher, vias can create significant resistance so use multiple vias to remove this issue.

Boost designs where the load can draw high currents can be very problematic.  Often the source is batteries where the voltage will drop as the load appears, or for low input voltages the power supply may need to be supplying high currents.  Once you build your prototype you may find that the say 3.0V to 5V @ 3A switch mode design which the switcher IC data sheet says will work just fine actually doesn’t.  So when designing these types of boost switch mode circuits you may want to consider:

Can you use multiple switch mode circuits to supply different loads, so that the power each has to output is reduced?  Often a problem switcher design will work fine if the load current is reduced.

Can you use a switchmode IC with an adjustable switching frequency?  If possible use one as it gives you an important parameter to adjust when trying to solve a problem.

Can you use 2oz copper on the PCB to reduce the resistance of power supply tracks?

Reduce the length of power input tracks.  If there is a risk that when you come to test your design it fails until you directly wire the power source to the inductor and mosfet consider this now and reduce the the track lengths the power input takes to get there and increase their copper width.  This is a classic problem!

Is there a chance you’ll need to increase input or output capacitance for the switcher – if you can add the footprints at the design stage just in case.  Remember that low ESR is often more important than capacitor size for switchmode supplies.

Could the tracking be improved in any way?  If so do it now instead of finding out the hard way!  If the switcher IC data sheet includes a recommended PCB layout does your layout match?   Could it?  Their layout works so if you can match it your chances of success are increased.

Read the switcher data sheet in it’s entirety.  Often there are hidden away mentions of additions to the recommended circuit useful in specific applications which may apply to your circuit.

Does the IC have an evaluation board?  If so read it’s data sheet to check if there is anything helpful in it you haven’t considered.

Solving Ground Bounce Problems

The primary cause of ground bounce is poor PCB design, or more typically non optimal PCB design.  These notes refer to boost switcher, but apply for a buck switcher also by adjusting for the different wiring arrangement.

A classic method to solving it is to start adding or changing capacitors, but this usually only has a very limited effect.

A good starting point to identifying the problem and curing it is to start by removing as many imperfections as possible:

Power the PCB with 0Vin connected directly to the switchers GND point, and with +Vin connected near to the inductor.

If the main capacitor is not connected ideally as above lift it and make it perfect using short wire links if necessary.

These two steps will give you a good starting point.  Has the ground bounce reduced or gone away?

Scope from the switchers GND point (mosfet ground) to the +V terminal of the main capacitor.  Is there noise?  There may be only a very short link but if you have noise between these two points then maybe you have the cause of your problem?  It might seem impossible for there to be noise from an inch of copper or wire, but it isn’t and if it’s there you need to eradicate it.

Check there isn’t an area elsewhere in the circuit causing or contributing to the noise by powering the PCB after the switcher (i.e. at its output so it’s no longer used).  Is the supply to the rest of the circuit now perfectly clean?

With the switcher powered again use a scope with its GND connected to the switchers GND point (DCDC converter IC power ground or external mosfet ground) and probe different areas of the PCB.  Does the noise level change depending on where you probe?  Probe to other GND points also.  If so this is likely to indicate areas of the circuit contributing to the noise.  What is the GND connection to that area like?  Does the noise reduce if you provide it with a direct dedicated GND connection to the switchers GND point?

Multilayer PCB 0V ground planes are great at reducing signal noise around a circuit, but are not necessarily great at reducing switcher ground bounce issues (as with audio they can often be a cause of new problems).  Should your power circuitry use a separate GND to the GND power plane or should the ground plane include some cuts to direct the switcher current? Don’t assume because there is a great big ground plane connecting to an area of the PCB that it’s therefore got a perfect GND connection.  Remember that true ground will be at one point of the PCB (i.e. at the 0V power connection in or at the GND connection of the switcher).  All other points returning current are not grounds but just return lines to ground.

Are there big capacitors elsewhere on the PCB that are affecting the switchers main capacitor being able to provide the perfect switch mode supply arrangement?  Are they part of the current path during switching?  Ensure the main capacitor is a low ESR (low impedance) type.

Does changing the switchers diode to a different part help?  It often shouldn’t but we’ve occasionally found that using a totally different model can sudenly cure much of a noise problem so it’s worth trying in case.  Remember that diode switching times are often only specified as a maximum value, not a typical.  Slower diodes can sometimes help.

Have a beer, then come back and read the switcher IC datasheet for a 10th time.  Hidden in the horrible technical detail may be something you’ve overlooked or that sparks a new process of elimination.  Get a piece of paper and draw out how you think the current is flowing in PCB traces.  Does that match the actual tracking and physical layout of the PCB?

Remember, the theory is sound but any PCB layout isn’t perfect.  The problem is being caused by something that isn’t perfect enough – you just need to work through every detail and find it.  If your new to switch mode design don’t worry, even experienced experts still get bitten by this stuff once in a while and the best way to learn the pitfalls is to find your way out of them – you only have to learn a mistake once.

More extreme solutions:

Should you completely isolate a sensitive area or the non high power area of the circuit?  Can you use a separate mains transformer winding or an isolated DCDC converter to power the other section of the circuit?  If you can this is often be a great solution.  You can then choose the one perfect point to connect the isolated GND rails.  Alternatively for more extreme issues should they remain isolated with opto isolated signals between them?

Ground Bounce Resources

You can never get your hands on enough ideas about solving ground bounce when faced with it!

http://www.analog.com/library/analogdialogue/archives/41-06/ground_bounce.html

http://homepages.which.net/~paul.hills/Emc/BecBody.html

http://www.edn.com/article/466994-Reducing_ground_bounce_in_dc_dc_converter_applications.php

• EMI & Signal Integrity checks:

Are there decoupling capacitors in all areas where there are connectors or via’s, to minimise EMI loop sizes of signals and their return ground path? If not do you need to add some? A power plane will act like the ground plane to high speed signals as long as the return signal can jump to the real ground plane through a nearby decoupling capacitor.

Ensure all high speed signal traces run over their own ground / power planes. Do not allow say a digital signal to travel over the analog plane unless it is going to a device in that area and in which case follow the devices digital ground trace to minimise the loop and therefore noise.

If there are any slots or gaps in the Gnd / Power planes ensure no high speed signals run over them (to avoid the return path having to loop round, creating EMI problems).

For high speed signals minimise track stubs (to below the critical length – ideally < 6.5mm, no more than 12mm for a 1ns rise time signal).

Ideally high speed connectors should have the ground plane getting through between pins to avoid signal return paths having to go round the connector to a ground pin on it.

Differential pair tracks are as close together as possible, or spaced based on impedance calculation?

Do any high speed signals need termination? This can be to VCC or Gnd and ideally should be at end of bus after the last receiving device. A good value is typically 50ohm, but anywhere from 30 – 100ohms is often fine. Should ideally match the impedance of the track.

• Add test points for important buses and connections to tight SMD chips so its easy to attach a wire or scope probe.

• Are power tracks big enough and do they have big enough via’s?

• Are there any very big through hole components such as elect capacitors?  If so don’t connect to internal layers on multilayer designs in case they get knocked and the internal connection is damaged.

• Check connections into power planes on >2 layer boards are big enough (enough via’s and big enough tracks).

• Check all important IC power pins have good decoupling capacitor connections

• Check crystal connections are short

• Do you need to add manufacturer test points (pads) for voltage rails etc?

• Are there components that need copper plane heatsinking (voltage regulators, mosfets etc)?

• Do you need to separate earth tracks from other tracks to avoid static problems?

• Are all jumpers, connectors etc labelled on the silkscreen?

• Check all surface mount pads have tracks that come out of the end, not the side (i.e. no links between adjacent IC pads that will look like a short during inspection).

• Do you need to add fiducial marks for the pick and place machine?

• Are there nets that need their length equalised (e.g. fast differential connections such as Ethernet)?

• Add a hatch fill done on both sides connected to GND to improve EMC?  These are a good general setting for the fill:- Track width: 0.3mm, Grid size: 0.6mm

• Create board outline on a mechanical layer

• Do a final design rule check

• Double check mounting positions will be OK in the equipment the PCB is fitted in.

The Problem

For example, a processor or microcontroller is wired to a SD memory card socket to allow it to access an SD memory card via its SPI port. When you try and communicate with the card you know your communicating correctly but the data received is incorrect and the driver doesn’t work correctly, either with the memory card failing to initialise or returning occasional or frequent bad data.

To make matters worse the problem may be sporadic, occurring randomly making tracking down the cause of the problem a nightmare.

Using a logic analyser to monitor the SPI data bus is a good way to try and track down the cause of a problem like this. However when this problem occurs you might find yourself scratching your head looking at the captured data, seeing that the commands sent to the memory card are correct but the data being returned by the card is wrong. Worse still the impedance of your probes may alter the problem causing it to vanish when the probes are connected, or alter its effect.

The Cause

Until relatively recent times digital PCB design (and especially when prototyping) could be viewed as simply a means to electrically interconnect components and unless you designed RF circuits there was little else to worry about. However the PCB itself, or the means of connecting the components used (i.e. prototyping), is now is a very common cause of a loss of signal integrity. The reason is mainly due to the rise and fall times of output signals having decreased as devices are designed to operate faster and faster and to use smaller and smaller silicon manufacturing processes. This problem is not actually due to the operating frequency of a device or the frequency at which a signal is changing, it is due to the speed at which a signal output changes state from high to low and low to high. A signal doesn’t instantaneously change from high to low or low to high, it takes a certain amount of time which will be specified as the rise and fall time in a devices data sheet. Previous signal rise and fall times of many 10′s of nano seconds have now become times measured in just a few nano seconds or for many devices they are measured in pico seconds.

So you may be thinking, this can’t possibly be an issue for me, my board is only operating at a few MHz and I’ve even slowed my data bus down to a few KHz. Well unfortunately that doesn’t matter. If you work with a DC signal the only thing you really care about in a wire or PCB track is its resistance, which for short lengths will be close to zero. However, when using that wire or PCB track with a fast AC signal it starts to behave like a capacitor and inductor. Capacitors and inductors exhibit resistance to alternating current called reactance. The impedance of the wire or track is the vector sum of resistance and reactance, essentially the total resistance seen at a particular frequency. What happens when you send a signal with a fast rising and falling edge down a wire or PCB track, if the impedance of the gate driving the wire or track isn’t exactly the same as the one receiving the it, is it that some of the pulse bounces (literally) back to the driving gate. As there is still an impedance mismatch, the signal continues to bounce between the two until it finally dampens out. This bouncing becomes worse as the speed of signal rise and fall times increases. Basically, the faster rise and fall times of signals from modern semiconductors combined with wire or PCB trace inductance and capacitance causes noise signals of a great magnitude than before. Greater magnitude means the bouncing signals can reach the threshold voltage required for the receiving device to ‘see’ another clock pulse, or an incorrect data level at the moment it is sampling the data line. This captured SPI bus clock transition illustrates the issue:-

(The timebase is 25nS per square, the voltages are 1V per square and the signals are being sent from a 5V powered microcontroller, to a VHCT125A IC which level converts down to 3.3V for a SD memory card.)

The pink trace is the SPI Data Out (DO) line from a SD memory card and the yellow trace is the SPI Clock (CLK) from a microcontroller. The yellow CLK goes low, the falling edge of which causes the SD memory card to change the state of its pink DO signal to high ready for the next rising clock edge which will clock the data bit into the microcontroller. However, due to CLK falling speed and an impedance mismatch the CLK signal bounces, causing it to rise above the minimum high input level requirement of the VHCT125A. The VHCT125A is a fast device so it faithfully passes the false high signal on to the SD memory card, which is also a fast device and it faithfully responds to the new clock signal, dropping the pink SPI DO signal as the next bit to send is low. End result, as you analyse what the card is returning to you at the microcontroller end it is completely baffling, but if you manage to capture the signals fast enough and at the right time you realise that the card is actually behaving exactly as it should and the problem is being caused by signal noise.

This problem has always occurred with digital signals, but with older semiconductors it could be largely ignored or was not even noticed as the bounce noise was not high enough to be a nuisance, or the recevieing device was not fast enough to detect a brief noise peek. However faster signal rise and fall times have increased the magnitude of this type of noise and devices have generally become faster and faster which now makes it a problem.

Solutions

Design your PCB to use 4 layers or more so you can provide a good ground plane. Using power planes in a PCB design can instantly solve all sorts of signal noise issues. Use impedance calculation tools to work out the correct PCB trace width for a signal in relation to the distance between the signal layer and the power plane layer.

If you can’t use a power plane then at least ensure you provide good ground trace routing. Many PCB designers spend ages optimising the routing of signals on their PCB’s and largely ignore the ground routing, forgetting that the routing of ground signals is 50% of the total path a signal takes.

Add a series resistor between the devices on important signal paths (e.g. 100 ohms – the ideal value is the sum of the resistor and the output impedance of the driver matching the impedance of the PCB trace). This is a popular method that doesn’t drain additional current, but is limited by the problem that the output impedance of a device is often different depending on the output state, and the need to know the PCB trace impedance.

Alternatively add a single terminating resistor to the far end of the PCB trace connected to GND or VCC with a value that matches the characteristic impedance of the trace. All of the energy flowing down the trace is absorbed by the resistor so there is no reflection. Alternatively a pair of resistors, one to GND and the other to VCC can be used. Commonly used values are 220 ohms for the resistor to VCC and 270 ohms for the resistor to ground, causing the trace to ‘see’ a parallel resistance of around 120 ohms. The downside of this is that the pair of resistors draw current so you could instead replace the resistor to GND with a small (couple of hundred pico farad) capacitor.

Once a bit of a black art, designing PCB’s to deal with signal noise issues of this type and many others is now a well understood subject and there are several very good books on the subject. One example is ‘Signal Integrity Issues and Printed Circuit Board Design’ by Douglas Brooks. Although quite mathematical in places if your not mathematically talented it still provides an excellent understanding of these types of issues.

Conclusion

This type of problem crops up all the time and is still often not well understood by both electronic and embedded software designers. Many designers simply give up and never get to the bottom of a problem application. Others find some sort of fix, say by ensuring they use a particular IC or device that seems to work. Often it’s the case its simply an older IC design that has slower signal rise and fall speeds or is slow to detect valid clock edges. Other designers spend ages trying to find the cause, eventually finding it by some clever scoping, or by re-designing their hardware with a ground plane or better routing to provide a more correct trace impedance and the problem disappears. By reading this you are now aware of the problem so the next time you hit a completely unexplainable problem you know what it might be. Hopefully though you’ll make sure you design your hardware better from the outset for pain free development and onward production.