The Cause

Until relatively recent times digital PCB design (and especially when prototyping) could be viewed as simply a means to electrically interconnect components and unless you designed RF circuits there was little else to worry about. However the PCB itself, or the means of connecting the components used (i.e. prototyping), is now is a very common cause of a loss of signal integrity. The reason is mainly due to the rise and fall times of output signals having decreased as devices are designed to operate faster and faster and to use smaller and smaller silicon manufacturing processes. This problem is not actually due to the operating frequency of a device or the frequency at which a signal is changing, it is due to the speed at which a signal output changes state from high to low and low to high. A signal doesn’t instantaneously change from high to low or low to high, it takes a certain amount of time which will be specified as the rise and fall time in a devices data sheet. Previous signal rise and fall times of many 10’s of nano seconds have now become times measured in just a few nano seconds or for many devices they are measured in pico seconds.

So you may be thinking, this can’t possibly be an issue for me, my board is only operating at a few MHz and I’ve even slowed my data bus down to a few KHz. Well unfortunately that doesn’t matter. If you work with a DC signal the only thing you really care about in a wire or PCB track is its resistance, which for short lengths will be close to zero. However, when using that wire or PCB track with a fast AC signal it starts to behave like a capacitor and inductor. Capacitors and inductors exhibit resistance to alternating current called reactance. The impedance of the wire or track is the vector sum of resistance and reactance, essentially the total resistance seen at a particular frequency. What happens when you send a signal with a fast rising and falling edge down a wire or PCB track, if the impedance of the gate driving the wire or track isn’t exactly the same as the one receiving the it, is it that some of the pulse bounces (literally) back to the driving gate. As there is still an impedance mismatch, the signal continues to bounce between the two until it finally dampens out. This bouncing becomes worse as the speed of signal rise and fall times increases. Basically, the faster rise and fall times of signals from modern semiconductors combined with wire or PCB trace inductance and capacitance causes noise signals of a greater magnitude than before. Greater magnitude means the bouncing signals can reach the threshold voltage required for the receiving device to ‘see’ another clock pulse, or an incorrect data level at the moment it is sampling the data line.  The solution is to design your PCB to use impedance controlled tracks on these clocked connections.

Single Connections

Download the free Saturn PCB Design Toolkit – its a great tool for this.  Use it as follows:

Select Conductor Impedance

Select Imperial or Metric (you can select later and it will auto convert all values)
Set copper weights and plating thickness (e.g. 18um copper + 18um plating = 35micros (1oz))
Select internal or external layers (typically microstrip or embedded microstrip)
Enter substrate options (prepreg dielectric constant – typical PCB’s are FR4)
Enter track width in conductor width
Enter prepreg height in conductor height (the distance between the copper layers excluding their thickness)
Click ‘solve’
Now adjust the track width until you get the impedance (Zo) you need.  This is the thickness to make your tracks

100ohm Single Track Impedance (General signals, SPI bus etc)

General signals, SPI bus, etc will generally perform well with a 100ohm track Impedance.  Some examples track widths with a GND plane under the tracks:

2 layer 1.6mm PCB (1.48mm FR4) = 0.61mm (100.3150ohms)

4 layer PCB Pool – Internal to Internal (0.71mm FR4) = 0.27mm (100.2273ohms)

4 layer PCB Pool – Internal to External (0.38mm FR4) = 0.12mm (100.9915ohms), or if too small then 0.15mm = (95.0631ohms)

4 layer PCB Train – Internal to Internal (0.99mm FR4) = 0.4mm (99.8636ohms)

4 layer PCB Train – Internal to External (0.22mm FR4, layer 2-3) = 0.05mm – not possible

4 layer PCB Train – Internal to External (1.245mm FR4, layer 1-3) = 0.49mm – not possible

75ohm Single Track Impedance

Also relevant to 75ohm radio antenna connections.Example track widths with GND plane under track

2 layer 1.6mm PCB (1.48mm FR4) = 1.29mm (75.0457ohms)

4 layer PCB Pool – Internal to Internal (0.71mm FR4) = 0.6mm (74.7938ohms)

4 layer PCB Pool – Internal to External (0.38mm FR4) = 0.3mm (74.8156ohms)

50ohm Single Track Impedance

Also relevant to 50ohm radio antenna connections.  Example track widths with GND plane under track

2 layer 1.6mm PCB (1.48mm FR4) = 2.65mm (50.1165ohms)

4 layer PCB Pool – Internal to Internal (0.71mm FR4) = 1.25mm (50.0581ohms)

4 layer PCB Pool – Internal to External (0.38mm FR4) = 0.65mm (49.9609ohms)

Differential Pairs

Download the free Saturn PCB Design Toolkit – its a great tool for this.  Use it as follows:

Select Differential Pairs

Select Imperial or Metric (you can select later and it will auto convert all values)
Set copper weights and plating thickness (e.g. 18um copper + 18um plating = 35micros (1oz))
Select internal or external layers (typically microstrip or embedded microstrip)
Enter substrate options (prepreg dielectric constant – typical PCB’s are FR4)
Enter track width in conductor width
Enter clearance between tracks in conductor distance
Enter prepreg height in conductor height (the distance between the copper layers excluding their thickness)
Click ‘solve’
Now adjust the track width and spacing until you get the impedance (Zdifferentail) you need.  This is the thickness to make your tracks

USB 90ohm Differential Pair Track Impedance

USB 2.0 requires 90ohms differential impedance (max 45ohms per track)

Max trace-length mismatch between High-speed USB signal pairs should be no greater than 3.81mm.

Example track widths with GND plane under track

4 layer PCB Pool – Internal to External (0.38mm height – FR4 thickness to GND plane)

35um copper, track spacing 0.15mm and 0.38mm track width = 90.525ohms Zdifferential
35um copper, track spacing 0.2mm and 0.43mm track width = 90.174ohms Zdifferential

To stick with the max 45ohms per track (not practical for many designs):
35um copper, track spacing 1.4mm and 0.75mm track width = 89.118ohms Zdifferential

4 layer PCB Pool – Internal to Internal (0.71mm height – FR4 thickness to GND plane)

35um copper, track spacing 0.15mm and 0.61mm track width = 90.385ohms Zdifferential

4 layer PCB Train – Internal to Internal (0.99mm height – FR4 thickness to GND plane)

35um copper, track spacing 0.15mm and 0.8mm track width = 90.156ohms Zdifferential

2 layer 1.6mm PCB (1.48mm FR4 thickness to GND plane)

35um copper, track spacing 0.15mm and 1.12mm track width = 90.184ohms Zdifferential

10/100Mbps Ethernet 100ohm Differential Pair Track Impedance

Ethernet requires 100ohms differential impedance (max 50ohms per track)

Example track widths with GND plane under track

4 layer PCB Pool – Internal to External (0.38mm height – FR4 thickness to GND plane)

35um copper, track spacing 0.15mm and 0.3mm track width = 100.462ohms Zdifferential
35um copper, track spacing 0.2mm and 0.34mm track width = 100.923ohms Zdifferential

To stick with the max 50ohms per track (not practical for many designs):
35um copper, track spacing 2.5mm and 0.65mm track width = 99.835ohms Zdifferential
If you use 1 of the plane layers with GND above and below (0.71mm & 0.38mm from track to GND planes) you get:
35um copper, track spacing 1.5mm and 0.42mm track width = 99.0.16ohms Zdifferential

Ensure Your PCB IS Made With The Right Stackup

Its a good idea to include the required stackup on one of your copper layers to ensure it is used.  Something like this:

• EMI & Signal Integrity checks:

Are there decoupling capacitors in all areas where there are connectors or via’s, to minimise EMI loop sizes of signals and their return ground path? If not do you need to add some? A power plane will act like the ground plane to high speed signals as long as the return signal can jump to the real ground plane through a nearby decoupling capacitor.

Ensure all high speed signal traces run over their own ground / power planes. Do not allow say a digital signal to travel over the analog plane unless it is going to a device in that area and in which case follow the devices digital ground trace to minimise the loop and therefore noise.

If there are any slots or gaps in the Gnd / Power planes ensure no high speed signals run over them (to avoid the return path having to loop round, creating EMI problems).

For high speed signals minimise track stubs (to below the critical length – ideally < 6.5mm, no more than 12mm for a 1ns rise time signal).

Ideally high speed connectors should have the ground plane getting through between pins to avoid signal return paths having to go round the connector to a ground pin on it.

Differential pair tracks are as close together as possible, or spaced based on impedance calculation?

Do any high speed signals need termination? This can be to VCC or Gnd and ideally should be at end of bus after the last receiving device. A good value is typically 50ohm, but anywhere from 30 – 100ohms is often fine. Should ideally match the impedance of the track.

• Add test points for important buses and connections to tight SMD chips so its easy to attach a wire or scope probe.

• Are power tracks big enough and do they have big enough via’s?

• Are there any very big through hole components such as elect capacitors?  If so don’t connect to internal layers on multilayer designs in case they get knocked and the internal connection is damaged.

• Check connections into power planes on >2 layer boards are big enough (enough via’s and big enough tracks).

• Check all important IC power pins have good decoupling capacitor connections

• Check crystal connections are short

• Do you need to add manufacturer test points (pads) for voltage rails etc?

• Are there components that need copper plane heatsinking (voltage regulators, mosfets etc)?

• Do you need to separate earth tracks from other tracks to avoid static problems?

• Are all jumpers, connectors etc labelled on the silkscreen?

• Check all surface mount pads have tracks that come out of the end, not the side (i.e. no links between adjacent IC pads that will look like a short during inspection).

• Do you need to add fiducial marks for the pick and place machine?

• Are there nets that need their length equalised (e.g. fast differential connections such as Ethernet)?

• Add a hatch fill done on both sides connected to GND to improve EMC?  These are a good general setting for the fill:- Track width: 0.3mm, Grid size: 0.6mm

• Create board outline on a mechanical layer

• Do a final design rule check

• Double check mounting positions will be OK in the equipment the PCB is fitted in.